A semiconductor wafer generally includes a “front” side having integrated circuits formed thereon, and a “backside” comprising a thickness of semiconductor material, such as silicon. Also formed in the wafer may be through silicon vias (TSVs). A TSV is filled with a conductive material, such as copper or tungsten, and the TSV is then sealed by a barrier layer to prevent the copper, tungsten or other metal from diffusing into the substrate. Prior to the dicing and packaging of the individual integrated circuit chips, the backside of the wafer is typically thinned to remove unwanted semiconductor material to allow for smaller packaging.
The thinning process is typically performed on the backside of the wafer by mechanical grinding and then chemical mechanical polishing (CMP). The CMP is continued until the thickness of the bulk silicon reaches a desired amount. Once this desired thickness is reached, the TSV is usually exposed. However, the exposed TSV typically diffuses copper or metallic contamination into the substrate, thereby deteriorating the overall performance of devices formed in the wafer and causing device failure.
For this reason and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved wafer thinning process that does not expose copper or other metallic contaminants from the TSV into the substrate.